Taiwan Semiconductor Manufacturing Company and Samsung Electronics, the world’s two largest chipmakers, announced on September 8, 2026, that they will adopt ASML’s High NA extreme ultraviolet, or EUV, lithography machines for advanced chip production. The move puts both companies on the same technology path as Intel, which has been the sole customer for this equipment since its 2019 debut, and it comes as demand for increasingly powerful AI chips pushes the entire semiconductor industry toward the outer limits of what current manufacturing technology can achieve.
Samsung plans to begin using High NA EUV machines for DRAM memory production in 2028. TSMC, which is the dominant manufacturer of custom chips for companies like Nvidia and Apple, plans to deploy the technology in high-volume advanced chip production starting in 2030. Each High NA EUV machine costs approximately $400 million — roughly double the price of the standard EUV machines currently used across the industry.
Why TSMC Was Reluctant Until Now
This shift is notable partly because of how cautious TSMC had been about the technology. The company had previously argued that the productivity gains from High NA EUV didn’t justify its steep cost, according to reporting on the announcement. That hesitation makes sense on paper: ASML’s own data, presented at the SPIE BACUS Photomask Technology conference where much of this announcement took place, shows that a phenomenon called “stitching” — a technical limitation tied to how the machines currently handle image projection — reduces High NA scanner output from roughly 175 wafers per hour to around 125, a productivity loss of nearly 30%. Paying twice as much for a machine that’s also less efficient per hour than expected is a difficult sell, even for a company as well-capitalized as TSMC.
What changed the calculus is a second, related announcement: TSMC, Samsung, and Intel have jointly committed to a new initiative called the Large Mask Consortium, aimed at replacing the 6-inch photomask standard that has governed chip manufacturing since the 1980s with a larger 12-inch format. ASML Chief Technology Officer Marco Pieters said the shift to larger photomasks — the physical stencils used to transfer circuit patterns onto silicon wafers — could boost High NA throughput by 40%, directly addressing the stitching penalty that had been undermining the technology’s cost case. “That’s a huge opportunity, and of course that means a significant step in productivity,” Pieters said.
A Long Runway Before Any of This Reaches Production
None of this technology is arriving quickly. The consortium is targeting a pilot line for 12-inch photomasks by 2031, with full High NA lithography readiness for advanced-node production by 2033 — meaning the productivity improvements that made this week’s commitments possible won’t actually be available in production for roughly seven more years. In the meantime, TSMC and Samsung’s near-term adoption plans (2030 and 2028, respectively) will rely on the current, less efficient version of High NA technology, accepting the stitching-related productivity loss as a temporary cost of getting a head start on the underlying manufacturing capability.
TSMC Chairman and CEO C.C. Wei framed the long-term collaboration in straightforward terms: “TSMC has always believed in the power of collaboration to overcome technical barriers before they become economic barriers for the semiconductor industry.” SK Hynix, the world’s second-largest memory chipmaker, is reportedly evaluating whether to join the consortium as well, which would bring all of the industry’s most significant manufacturers onto a shared technical roadmap.
What’s Actually Driving the Urgency
The underlying force behind all of this is straightforward: demand for AI chips has been growing faster than the industry’s ability to manufacture them at the transistor densities modern AI accelerators require. TSMC reported July revenue of NT$467.58 billion, up 44.7% year-over-year, and has raised its full-year 2026 capital expenditure projection to between $60 billion and $64 billion specifically to keep pace with that demand. Samsung’s semiconductor division has posted similarly strong results, with the company’s overall market capitalization crossing $1 trillion earlier this year, driven substantially by memory chip demand tied to AI infrastructure spending.
High NA EUV machines matter in this context because they enable denser transistor packing than any previous generation of lithography equipment — a critical requirement for the next generation of AI accelerator chips, where performance per watt of power consumed directly determines data center operating costs. Intel, which adopted the technology earliest, has already used it to build more than a million wafers on its 18A manufacturing process for select Core Ultra Series 3 processors, and the company is developing a follow-up version, 18A-P, that’s reportedly under consideration by Apple for a future generation of iPhone processors.
What This Means for the Broader Chip Shortage
For ASML, these commitments extend the company’s order visibility well into 2027 and beyond, reinforcing its position as the sole supplier capable of building EUV lithography equipment at all — a genuine monopoly in one of the most critical bottlenecks in modern chip manufacturing. For the broader semiconductor industry, this represents a multi-year capital spending commitment that should eventually expand the total manufacturing capacity available for advanced chips, though not on any timeline that offers near-term relief. TSMC’s 2030 timeline and the 2033 target for full technology readiness both fall well after the current memory chip shortage — which industry executives like SK Hynix’s CEO have separately projected could persist through 2030 — is expected to ease.
What This Means for Everyday Tech Buyers
For consumers, this announcement won’t change anything about device prices or availability in the near term — the manufacturing capacity being planned here won’t come online until the end of the decade at the earliest. What it does signal is that the world’s most capable chipmakers are committing serious capital toward solving the underlying manufacturing bottleneck behind the current AI chip and memory shortage, rather than treating it as a temporary supply hiccup. That’s a reasonable, if distant, sign that today’s elevated component costs and constrained chip supply reflect a structural industry transition rather than a problem likely to resolve itself quickly through existing manufacturing capacity alone.
